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5.4 GOPS, 81 GB/s Linear Array Architecture DSP
5.4 GOPS, 81 GB/s Linear Array Architecture DSP
1998
Hiroshi Okuda
Koji Aoyama
Mitsuharu Ohki
Katsunori Seno
Ichiro Kumata
Masatoshi Aikawa
H. Hanaki
Akihiko Hashiguchi
Masuyoshi Kurokawa
Kenichiro Nakamura
Keywords:
Parallel computing
SIMD
Parallel processing
Digital signal processing
Architecture
Computer science
Computer hardware
linear array
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