Power Cycling of Three-Level Inverters for Low Speed Operation

Low speed operation of inverters can cause high maximum temperature that results in the necessity of over rating design of power modules. Operating the converter in fundamental frequencies higher than zero can have worse results than the DC output due of the high temperature ripple. Temperature ripple can stress the bond wires and chips. This paper investigates the possibility of using different topologies (two- level and three-level) and semiconductor types for lowering losses and distributing the losses between the power semiconductors.