A special purpose parallel processing ASIC for the first-level calorimeter trigger for the ATLAS detector

Modern high energy physics experiments require massively parallel special purpose computers (triggers) to reduce the extremely large primary data flow to manageable amounts. We present a prototype processing ASIC intended as the basic computational unit in a first-level calorimeter trigger for the ATLAS collider detector to be built at CERN, Switzerland. The proposed trigger is a compact highly parallel pipelined system with 4096 systolic processors partitioned into 256 weakly-interacting custom-designed ASICs. Local results from these ASICs are then merged by a second, less complex type of ASIC. Data is received at 800 Mbit/s by bipolar input circuits, while the processing is performed in CMOS at 320 MHz, using the true single phase clocking scheme (TSPC). This method promotes fast and compact implementations well suited for pipelined bit-serial applications. A 0.5 /spl mu/m BiCMOS process with 4 metal layers was chosen for the implementation.