Heterogeneous Integration Solutions for HPC Application by Using FO-MCM Chip Last Platform

For years high performance computing (HPC) products have been integrating more and more functions in the IC. Large die size with high density transistor is still the trend for IC product design, especially networking and CPU product. As Moore's law nears its physical limits, split die and heterogeneous integration in package are the effective solution to increase gross die and wafer yield for cost saving. In order to fulfil electronical performance, line width/ space small than 5/5um is necessary for die to die high density IO interconnection. Currently, 2.5DIC package is one of the mature solutions for fine line interconnection in the industry. Besides, fan-out multi-chip module (FO-MCM) is an alternative technology with low cost benefit that uses redistribution layer (RDL) instead of silicon interposer. For different segment of applications, FO-MCM chip last and chip first platform are widely used in industry. Chip last process has lower thermal budget on die, no die loss due to know good RDL and shorter cycle time advantages, which is ideal for applications requires multi dies as well as fine RDL interconnections. However, it still has the warpage control challenge with bump non-wetting/ bridge concern, due to the mold grinding process on FO module with complex composition (chip with ubump, underfill and compound). In this study, we will address the package warpage performance and the relationship of FO final thickness by FO-MCM chip last process. Finally, we will demonstrated three layer RDL structure and minimum line width/ space down to 2/2um. Package level reliability qualification is also finished with temperature cycle test (TCT), unbiased highly accelerated stress test (uHAST) and high temperature storage life (HTSL) conditions.