Architectural Structures in ISA Design

This chapter forms a bridge between certain ISA-wide architectural issues and the ISA-invisible microarchitectural techniques. It discusses the most distinguishing topics in the design of a VLIW ISA, and in particular it discusses many of the common hardware structures (and the operations that drive them) within the ISA. It begins with the datapath, the heart of any processor core. Datapath design includes the types of execution units, the widths of the data lines, and the common arithmetic and logic operations performed by the core. The chapter also discusses registers and clusters. Clusters are intimately related to the datapath, but can be considered the next level of design “above” the datapath level. Memory architecture includes considerations of addressing modes, access size, alignment issues, and the effect (and visibility) of caches and the memory hierarchy. Branch architecture includes deconstructing branches into their fundamental components, handling multiway branches, handling branches in clustered architectures, and handling branches in loop-dominated code. The chapter also discusses speculation and predication, high-performance techniques that might be seen as questionable in the embedded domain. The last section of this chapter describes system operations. System operations are all of the complicated maintenance- and security-related work required for building a real system, but these are also briefly mentioned except in hardware reference manuals.