Shallow trench isolation double-diobe electrostatic discharge circuit and interaction with DRAM output circuitry
1993
Abstract Electrostatic discharge (ESD) performance of a shallow-trench-isolation double-diode protection circuit in CMOS technology is discussed. This paper highlights the sensitivities of these devices to semiconductor process parameters, interaction with chip circuitry and advanced failure analysis techniques.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
12
References
28
Citations
NaN
KQI