FinFET with double gate silicon layer for chemical mechanical Poliereinebnung

A process for producing a semiconductor device, comprising: Forming a fin structure (210) on an insulator; Forming a gate structure over at least a portion of the ridge structure and a part of the insulator, wherein the gate structure comprises a first layer (420) and a second layer (425) formed over the first layer; and Planarizing the gate structure by performing a chemical mechanical polishing (CMP) of the gate structure, wherein the planarization rate of the first layer (420) of the gate structure is less than that for the second layer (425) of the gate structure, and wherein said planarizing is continued until an upper surface of the first layer is exposed in an area over the web.