System Co-Design Modeling Methodology of a High Speed (25Gbps) Multi-Rate 4-Channel Retimer: Simulation to Measurement Correlation

Abstract In this paper we detail the system (viz. silicon-package-pcb) electrical co-design of a 130nm BiCMOS high-speed (25Gbps) 4-channel multi-rate retimer, packaged in a small 6-mm × 6-mm FC BGA package, with integrated advanced signal conditioning circuitries. Electrical optimization of the silicon-package-pcb over the high speed channels, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Key figure of merits for system electrical performance (viz. insertion loss, return loss, crosstalk/isolation, jitter, and power supply inductance and resistance parasitics, among others) are modeled and analyzed. Laboratory measurements on a retimer are presented that validate the integrity of the modeling methodology. Good correlation between modeling methodology and laboratory measurements is achieved.