Multi-level parallelism analysis and system-level simulation for many-core Vision processor design

The technology convergence and the evolution of embedded systems to multi/many-core architectures allow envisioning future cameras as many-core systems able to process complex Image Processing and Computer Vision (IP/CV) applications. IP/CV algorithms have natural parallelism which must be efficiently explored to meet embedded application's constraints (real-time, power consumption, silicon area, temperature management, fault tolerance, and so on). In the case of many-core architectures, the efficiency comes not only from the number and type of processing cores but how they communicate and how the memory is organized. In this work, we show a multi-level parallelism study of IP/CV algorithms/applications, analyzing how to explore the different features available in many-core architecture's design space. The analysis is performed using a high-level SystemC/TLM2.0 platform specially developed for this task. As results, we propose a hierarchical parallelism extraction, a transparent programming model and a many-core architecture template for the next generation of vision processors.