500-Mb/s nonprecharged data bus for high-speed DRAM's

A nonprecharged data-bus scheme to enhance the intrinsic read data rate of DRAM cores is proposed. Eliminating the precharge cycle of the DRAM data bus can reduce the unit bit time. A differential partial response detection data-bus amplifier is also employed to detect signals on the nonprecharged data bus that are degraded by large intersymbol interference. To enhance the read operation further, column selections are overlapped by interleaved column decoders. To increase the operating margin of the nonprecharged data-bus read, a skew-controlled column-selection pulse generator was developed. An isolated sense-amplifier scheme increases the write data rate of the DRAM core. To verify these schemes, a 4-Mb DRAM was fabricated via 0.24-/spl mu/m DRAM technology. These schemes realized a 500-Mb/s per data-bus read operation and a 100-Mb/s per data-bus write operation without an area penalty.