Design of Hybrid Pulsed FlipFlop Featuring Embedded logic

This paper introduces a novel power efficient hybrid pulsed flip-flop (HPFF) with embedded logic module (HPFF-ELM) based on transmission gate scheme. The HPFF possess a hybrid architecture that combines the merits of dynamic and static structures. The performance of modern high performance flip-flops are compared with that of HPFF at different data activity. The proposed HPFF architecture is power efficient and has the ability to incorporate logic functions into the flip-flop which forms HPFF-ELM. The performance comparisons and analysis is made in TSMC process using mentor graphics EDA tool. The HPFF and HPFFELM is compared with other state-of-the-art design. The performance improvements indicate that the proposed designs are well suited for modern high-performance circuits where power dissipation and area overhead are of major concern.