11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET

Interest in ultra-high-speed wireline communications targeting 100Gb/s+ is rapidly increasing to accommodate the massive data traffic of data centric systems such as Internet-of-things, autonomous driving, cloud computing, etc. In recent publications, a 14GHz LC-PLL was successfully demonstrated for 112Gb/s PAM-4 transmitter clocking [1–3]. To extend the data rate to 224Gb/s, a 28GHz LC-PLL can be adopted instead of increased interleaving or use of higher-order modulation (PAM-8/16). However, doubling the PLL clock frequency without jitter or power penalties is challenging because doubling the data rate requires a 50% jitter reduction while CML-to-CMOS buffer and prescaler divider have increasing power overhead as they are pushed closer to millimeter-wave (mm-wave) frequency ranges. This paper presents a 23.9-to-29.4GHz digital LC-PLL architecture that achieves a 65fs random jitter measured at a transmitter output with 17.1mW power consumption. The proposed design uses: 1) a current re-use coupled frequency doubler oscillator to improve phase noise by 4.5dB compared to a conventional LC-DCO with only a 25% power increase; 2) an automatic frequency-tracking loop (FTL) to optimize the phase noise of the frequency doubler across PVT; and 3) power saving by avoiding the prescaler divider operating in mm-wave frequencies.