A 12-bit 10GSps ultra high speed DAC in InP HBT technology

In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz f T 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.