A Paralleled Greedy LLL Algorithm for 16×16 MIMO Detection

This brief proposes a paralleled greedy Lenstra-Lenstra-Lovsz (PGLLL) algorithm for 16×16 MIMO detection. First, a paralleled constant-throughput scheme is designed for LLL algorithm. Then, greedy algorithm is adopted on this scheme to select the most urgent iterations for each stage. This selecting criterion outperforms others in that numerous iterations can be concurrently selected to reduce latency, and that the two factors of LLL potential and MIMO detection strategy are comprehensively considered by this criterion to improve bit-error-rate (BER) performance. Simulation indicates that the PGLLL can realize a comparable performance to the non-greedy algorithm and LLL algorithm with less iterations. Finally, this brief is the first to propose a hardware architecture with greedy LLL algorithm. This architecture is implemented with 65-nm 1P9M CMOS technology, which can work at a maximum frequency of 625 MHz to process 16×16 complex-valued matrices every 16 clocks. The latency is 362 ns. Comparison indicates that the proposed PGLLL architecture is superior to other existing works in terms of throughput and latency performance.