Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology

This work presents the layout area of encoded and decoded multiplexers, two essential building blocks of modern FPGAs, in FinFET. Layouts with both 2 and 3 metal layers based on ASAP7 Predictive Design Kit are presented. The layout area is then compared with the prediction of two equation-based models: the VPR area model and the COFFE area model. We found that, with the original model parameters which are adjusted for planar technologies, these two equation-based models are not accurate in predicting FinFET layout area with error ranges of -2.3% to +86.5% and -32.7% to +19.3% for the VPR and COFFE models, respectively. Furthermore, when the model parameters are specifically adjusted for FinFET, the error ranges remain to be large with -19% to +31% and -26.6% to +25% for the VPR and COFFE models, respectively. These data underline the importance of verifying equation-based models against actual layout areas in FPGA architectural studies, especially when there are significant changes in the underlining process technologies.