Modeling and analysis of leakage power considering within-die process variations

We describe the impact of process variation on leakage power for a 0.18 /spl mu/m CMOS technology. We show that variability, manifested in gate length (L/sub drawn/), gate oxide thickness (T/sub ox/), and channel dose (N/sub sub/), can drastically affect the leakage current. We first present Monte Carlo-based simulation results for leakage current in various CMOS gates when the process parameters are varied both individually and concurrently. We then derive an analytical model to estimate the mean and standard deviation of the leakage current as a function of the process parameter distributions. We demonstrate that the results of the analytical model match well with Monte-Carlo simulations and also show the statistical mean leakage current is significantly different from the leakage predicted using a nominal case file.