Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement

Performance degradation tolerance (PDT) is a new notion that can improve the effective yield and reliability of designs. The basic idea is that defective chips that contain a special type of faults can still functionally work but with some performance degradation. This type of faults is called performance degrading faults (pdef). As long as the performance of defective chips containing pdef is acceptable for some applications, these chips may still be marketable. In the literature there have been several works addressing applications of this notion. However these works mainly focus on addressing some aspects of the PDT notion, such as tolerability analysis or enhancement. Also, one specific application is usually targeted, such as branch predictor. There is still a lack of a general and complete flow to apply the PDT notion. Although there is a number of common issues shared by these works, no work in the literature summarizes general rules from these works for application to a new design. In this work we develop a systematic methodology to guide users applying PDT to their designs step-by-step. Issues in each step of the methodology are discussed and illustrated using the available methods in the literature. Furthermore, we also employ value predictors that have not been targeted in the literature to demonstrate how the proposed methodology is applied to a new application.