System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the system-level performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.