A reconfigurable test method based on LFSR for 3D stacking integrated circuits

The specificity of the 3D integrated circuit and the changes in the design integration flow bring many new problems to the test process, such as reducing the controllability of the test and increasing the test cost. To address these problems, this paper proposes a low-power hybrid test scheme based on multiple reconfigurable linear feedback shift register(LFSRs) for 3D integrated circuit, which can reuse the test vector generator of the pre-binding test phase in the in-binding and post-binding test phase, reconfiguring a new test vector generator with lower test cost. Compared with the method of using the linear feedback shift register(LFSR) of each layer circuit independently as the test vector generator of the whole circuit in the in-binding test phase, the scheme in this paper can effectively utilize the original LFSR of each layer circuit and reduce the area overhead; the reconfigured 3D-LFSR can obtain better test data compression effect and lower test power consumption, improve test efficiency and reduce test time. Experiments have shown a 5% improvement in average test data compression, 53.1% and 9.6% reduction in average and peak power consumption respectively, 28% reduction in test area and 19.6% reduction in test time.