All-Digital Successive Approximation TDC in Time-Mode Signal Processing

An 8-bit time-mode successive approximation register time-to-digital converter (SAR TDC) is proposed. The TDC achieves a high resolution and a better power/area efficiency by using a pre-skewed delay line with digital time interpolation. The impact of pre-skewing on delay and power consumption is investigated. A cascode inverter interpolation cell with improved input-output isolation is introduced. The impact of the slope of input signals on the linearity of the time interpolator is investigated. Timing errors caused by device noise are quantified. The SAR TDC is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the SAR TDC operated at 10 MS/s achieves 0.33 ps solution, 9.68 ENOB, and 0.20 pJ/conv. FOM.