Illegal state space identification for sequential circuit test generation

Here our new techniques are proposed to expand the known Global Illegal State (GIS) space, in order to reduce the search space. These techniques use the known GISes to generate candidate GISes, which have to be proven unjustifiable. This is an effective method to improve STPG performance because the number of stored GISes is reduced, saving memory and CPU time, while covering a larger part of the GIS space. To accelerate GIS space identification, we propose the legal state cache, to avoid useless justification repetitions. A data-structure is proposed to reduce the memory usage of the (G)ISes up to 10 times, and to accelerate GIS usage. Experimental results show a significant improvement in fault efficiency and CPU usage.