Near Data Computation for Message-Passing Chip-Multiprocessors

As the CMP (Chip-Multiprocessor) scale increases' moving data to computation becomes more and more expensive in terms of latency and energy consumption. Conversely, the scheme of moving computation to data has potential to improve efficiency, especially for the irregular applications that contain graph computing, hash map or matrix multiplication. This paper proposed a near-data processing scheme for the large scale CMPs with hardware message passing support, which we called in-place computation scheme. In the in-place computation scheme, an application's critical irregular data is partitioned into on-chip memory-slices and each slice is managed by an adjacent core, as any other core intends to operate such data, it sends a message to the data owner to process it, rather than fetching the data back for computation by itself. In the paper, we described the programming model, hardware/software requirements and optimization strategies of the in-place computation scheme in details. Simulations show that, compared with conventional implementations, it can improve the performance and energy-efficiency significantly in most cases, due to following factors: 1) It greatly reduces data movements and synchronizations, 2) It decreases core-pipeline stalls and improves efficiency of memory-accesses.