Better-Than-DMR Techniques for Yield Improvement

In this work, we first study LUT optimization in PPCs for increasing their area-efficiency for yield improvement. We focus on the fact that although 2 ²ⁿ configurations are available for an-input LUT, such full programmability is not needed, i.e., one configuration is enough for bypassing one specific fault. Then, we optimize away too rich programmability of LUTs exploiting application features in order to reduce the area cost without degrading the fault bypassability from the original PPC.