Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques

In advanced technology nodes, the process variations deteriorate SRAM performance and greatly affect yield. It is necessary to formulate yield estimation models to optimize SRAMs and effectively trade-off area, performance and robustness. We propose models that in addition to enabling yield estimates also enable evaluation of lowering minimum operational voltage (VDDMIN). We present a quantitative analysis for SNM limited SRAM yield using Design of Experiments (DOE) method. The proposed framework for yield based design can also utilize recovery techniques like Error Correcting Codes (ECC) and redundancy and quantifies yield, area, and VDDMIN improvements. We also present a case study that trades-off ECC recovery budget, VDDMIN and area gain. We show 25% improvement in area and VDDMIN lowering by 300mV at constant yield levels by using 50% of ECC recovery budget.