Design of a filter bank multi-carrier system for broadband power line communications

A semi-parallel architecture to implement a filter-bank multi-carrier system for broadband communications is presented. The signal processing schemes for both the transmitter and the receiver have been analyzed in terms of computational complexity, thus determining the corresponding requirements and constraints to be considered in the definition of architecture parameters, such as internal data rates or operation frequencies. Furthermore, the proposed design allows to achieve a real-time implementation of the whole transmultiplexer for broadband multi-carrier communications in a Field-Programmable Gate Array (FPGA) device. This implementation has been carried out by means of a System-on-Chip (SoC)-based architecture, where the specific hardware for the transmultiplexer has been integrated as an advanced peripheral. For experimental tests, all the architecture description has been particularized for a transmultiplexer configuration recommended by the IEEE 1901 working group for broadband power line communications. Nevertheless, the designed architecture can be easily adapted to other options by suitably defining some generic parameters in its HDL (Hardware Description Language) specification.