Comprehensive analysis and optimization of CMOS LNA noise performance

Comprehensive analysis of CMOS low noise amplifier (LNA) noise performance is presented in this paper, including channel noise and induced gate noise in MOS devices. The impacts of distributed gate resistance and intrinsic channel resistance on noise performance are also considered and formulized. A new analytical formula for noise figure is proposed. Two kinds of noise optimization approaches are performed. This work will benefit the design of high performance CMOS LNA.