Conditional pre-charge techniques for power-efficient dual-edge clocking

A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18/spl mu/m process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.