Test methodology for the McKinley processor

The McKinley processor is the result of a joint design effort between Intel and Hewlett-Packard engineers, and is the second processor implementation of the Itanium/sup TM/ processor family (IPF) architecture. This paper describes the methodology developed for testing a complex high-performance microprocessor design. An overview of the processor is presented, along with the goals for the test methodology. Details of the test control blocks, scan methodology, and clocking are given. The scanlatch design, trade-offs and verification processes are discussed, along with some details of ATPG modeling and memory array testing. Finally, some results are presented.