Compact MAX and MIN Stochastic Computing architectures

In this work we present Stochastic Computing MAX and MIN architectures. Their operation relies on an accumulator to store the signed-bit differences between their two stochastic input sequences without additional randomization. This counting process makes their operation deterministic, resulting in an improved latency-accuracy trade-off when compared to existing Stochastic Computing MAX and MIN architectures. Modeling the architectures as Markov Chains allows for an in-depth analysis of their stochastic operation, derivation of their statistical properties and proof of their correct operation. An overflow/underflow Markov Chain model allows for the analytic calculation of the register size they use, providing guidelines for its selection based on accuracy requirements. The performance of the proposed architectures is compared to those of existing ones in the Stochastic Computing literature in computational accuracy and hardware resources using MATLAB and Synopsys Tools. Their effectiveness is demonstrated in two standard Digital Image Processing tasks; image denoising with a 3 × 3 median filter and dimensionality reduction of an image with a 2 × 2 max pooling kernel.