Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs

Effective bug localization during verification is a challenging step in the development cycle of complex hardware designs. While meeting different coverage goals is possible in the verification process, yet bug localization cannot be directly related to such goals. We propose a two-step methodology to achieve fine-grained design bug localization. First, we obtain multiple error traces based on a failing property. Starting from an initial error trace, we employ model checking to generate supportive error traces that are utilized to mine important assertions. In the second step, we utilize these assertions for fine-grained design bug localization. The mapping of the assertions leads to specific regions in register transfer level descriptions that are highly probable to be the root cause of the design bug. Specifically, we devise a binning methodology to categorize multiple suspects in different bins that need to be investigated by the design engineer for arriving at the correction for corresponding bugs. Experiments on multiple designs illustrate the efficacy of the proposed methodology in comparison to previous work and state-of-the-art industrial tool.