High-performance ( $\text{EOT} , Jg∼10 −7 A/cm 2 ) ALD-deposited Ru\SrTiO 3 stack for next generations DRAM pillar capacitor

We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10 −7 A/cm 2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO 3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.