Redundant SAR ADCs with Split-capacitor DAC

This paper proposes a unified formulation for Successive Approximation Register (SAR) ADCs with split-capacitor arrays and provides explicit expressions for the relationships between capacitors and the weighting coefficients in the digital correction logic. Thanks to this formulation, a study of the voltage excursions in the arrays can be carried out for ADC schemes without or with redundancy. Also, the closed-form expressions result suitable for design decisions allowing the estimation of the optimum limiting capacitor that controls the voltage excursion in the floating node of the Least Significant Bit (LSB) capacitor array. The proposed hardware-based formulation has been verified by behavioral and electrical simulations.