Capturing intrinsic impact of low-k dielectric stacks and packaging materials on mechanical integrity of Cu/low-k interconnects

We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types of packaging, from low-cost QFPs to high-performance Pb-free FCBGAs.