FPGA Implementatıon of Turbo Product Codes for Error Correctıon

This paper aims to design and implement the very efficient turbo product codes decoding technique for errorless signal reception. The turbo product codes (TPC) are finding a wide range of applications in the communication field where ever highest data rate is required is selected for the design. The message is encoded to form the TPC such that a k × k message will be converted into an n × n TPC. The signal is transmitted through the AWGN channel. Iterative Chase-Pyndiah type 2 decoding algorithm is followed in the decoding section. This decoding technique can decode the transmitted codeword with very much less probability of errors as well as have a very low decoding complexity and is also efficient in achieving the highest data rate. The (n, k, d) hamming codes are selected for the design, because of its properties like the highest code rate, ability to correct the single-bit error and identify multiple bit errors. The hardware is implemented in the Xilinx FPGA platform.