Clock-Gating in FPGAs: A Novel and Comparative Evaluation

Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process. For a set of design cases, both the FPGA and ASIC clock-gating methods were implemented. Figures of power consumption were obtained using the corresponding FPGA/ASIC power estimation tools and devices. The results show that in FPGAs, the efficiency of savings in dynamic power consumption is about 50% to 80% of its ASIC counterparts. However, we also found that compared to ASICs, clock-gating for FPGAs in terms of the efficiency of savings in total average power consumption was only about 6% to 30% of its ASIC counterparts due to FPGA’s large static power consumption.