The impact of self-heating and its implications on hot-carrier degradation – A modeling study

Abstract A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with confined architectures, such as fin and nanowire (NW) FETs. Although the view on whether SH accelerates or inhibits HCD in n-channel devices is controversial, it is commonly accepted that in p-channel FETs HCD becomes more pronounced due to SH. Therefore, we develop a framework for modeling coupled HCD and SH and validate it against experimental data acquired in p-channel Si NWFETs. This framework incorporates a carrier transport solver linked to a solver for the lattice heat flow equation; the latter solver allows one to evaluate a non-uniform lattice temperature distribution in the device. Carrier energy distribution functions obtained considering coordinate-dependent lattice temperature are used to calculate the rates of the multiple- and single-carrier processes of Si H bond dissociation. In addition to perturbation of carrier transport by SH, elevated lattice temperature results in enhancement of the thermal contribution to the bond rupture rate and shortens vibrational lifetime of the Si H bond, thereby reducing the multiple-carrier process rate. All these three aspects are captured by our framework, importance of each of them is analyzed, and our approach was shown to accurately reproduce experimental data.