Deterministic test generation for digital circuits by cellular automata in a Java applet
2003
The paper presents implementation of a test pattern generation algorithm that uses cellular automata with bit flipping to generate a pre-computed test set. The algorithm is realized as a Java applet for automatic synthesis of the built-in self-test structure into a digital circuit modeled in VHDL using only its VHDL entity. This software tool is available on the Internet.
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