High Performance HVNMOS Development for Advanced Planner Nand Flash

As the flash cell physical size is scaled down, the related down scaling of decoder and page buffer area are also a challenge for chip design. High performance N type MOS including HVN_PT (in word-line decode circuit) and HVN_PB (in page buffer circuit) for l×-nm planner NAND flash are described in this paper. These N type MOS adopted a series of optimized structure and process integrated methods based on 2D TCAD process and device simulation, to achieve high channel, junction breakdown, and isolation voltage with smaller transistor area limited by down scaled NAND flash cell unit. Finally, these structure and process integrated methods were validated in HLMC 12-inch l×-nm NAND process flow.