National Chip Implementation Center, National Applied Research Lab, Hsinchu, Taiwan

This paper presents a 43 GHz divide-by-three prescaler implemented in 0.13µm CMOS technology. The variation of regenerative topology is used to perform frequency division by three at millimeter-wave frequency. The band-pass filtering is developed with circuit parasitics to suppress unwanted harmonics. By combining the Gilbert-cell mixer and differential injection locked oscillator, the maximum operating frequency of the CMOS divide-by-three prescaler is elevated to 43 GHz. The measured phase noise is -108.8 dBc/Hz at 1MHz offset from the output signal frequency. Operated at 2V, the prescaler consumes 16mW of power. The total chip size is 0.8 × 0.6 mm 2 .