Research of 100 MHz ultra-low-jitter clock generating circuit

Jitter which quantifies the quality of a clock is an important specification. It is of great significance for an electronic system. To obtain a good signal-to-noise ratio for sampling systems, there must be clocks with low jitter performances. By using the relationship between jitter and phase noise, the 100 MHz clock generating circuit with ultra-low jitter and phase noise characteristics are studied in this paper. Bipolar junction transistor with low noise figure and low corner frequency should be selected. Inductance and capacitance in the feedback circuit are obviously the main contributions to the jitter. Impacts of the loaded quality factor (QL) of the circuit on the jitter are analyzed, and the explicit expression for the jitter based on circuit components is derived as well. The simulation and experiment results are proved to show that the jitter and phase noise characteristics can be improved by increasing QL of the circuit.