MOS gated device base region with high breakdown resistance

An n + drain layer 2 and an n - layer 1 on n + drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n - layer 1. An n + source region 6 is formed in the surface portion of p-type base region 3. A p + region 5, deeper than n + source region 6 and shallower than p-type base region 3, partially overlaps n + source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n + source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n - layer 1 and n + source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p + region 5 and n + source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n + drain layer 2. A junction face 20 of p-type base region 3 and n - layer 1 has a finite radius of curvature such that the depth from the surface of p + region 5 to junction face 20 is deepest beneath the center of p + region 5.