An introduction to the SystemC synthesis subset standard

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. OSCI's synthesis working group (SWG) [3] has led the effort of defining the synthesis subset for SystemC that is suitable for HLS. Draft version 1.3 [4] of the document was released for public review in August 2009. While still in draft form, the released document provides guidance to both tool providers and users on the subset that is being proposed and the ability to provide feedback to the SWG on the draft. This tutorial will provide a brief introduction and three case studies on the use of HLS and the current SystemC synthesis subset draft for hardware design of digital systems