Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture

Phase-locked loop (PLL)-based frequency synthesizers are pervasively utilized in almost every electronic system for generating welldefined clock frequencies of interest. For instance, in a modern wireless transceiver, a radio-frequency (RF) synthesizer is typically used as a local oscillator to upconvert/downconvert the desired signal to and from the proper communication bands. A similar utilization of RF PLL can be seen in a wireline transceiver, which modulates and demodulates the data symbol at a precise frequency and phase. In addition to RF applications, PLL is also commonly used in baseband and digital circuitry, such as generating a sampling clock for switched-capacitor circuits and clocking the sequential logic of the digital circuitry. As the complexity of the modern system-onchip (SoC) platform continues to grow, it is likely to require numerous highperformance PLLs. Moreover, interference coupling through the same silicon substrate is exacerbated. As a result, the low implementation (area and power) cost, high reconfigurability, resilience over interferences, and reduced design time of a PLL have become increasingly important in light of this new trend.