Procedure and Loop Level Speculative Parallelism Analysis in HPEC

Although High Performance Embedded Computing(HPEC) has been effectively analyzed on different platforms, there is still room for an in-depth analysis of thread level speculation (TLS), especially at the procedure level. This paper explores the potential parallelism of HPEC from procedure and loop level TLS techniques, and designs the corresponding analysis mechanism and data structures. Our aim is to show the improved performance of various applications used in HPEC. Results from our experiments demonstrate that: 1) the performance of all applications was relatively good, the best tdfir application achieves 221.8x speedup in procedure level speculation whilst a ct application gets a 13x speedup in loop level speculation; 2) HPEC programs can be accelerated by effectively utilizing the computing resources of 16 to 32 cores; 3) Applications, that contain multiple non-severe data-dependency procedure calls, are more suitable for developing parallelism using procedure level TLS technology.