Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

2.5D packages have been widely used in electronics industry for high performance and product miniaturization. As Through-Silicon-Via (TSV) fabrication methods and multi-level assembly technologies get mature, 2.5D packaging becomes reliable and affordable. In this work, board-level life prediction was performed for a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling. Finite element models were built and validated by warpage measurement. Solder fatigue life in power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis. Improved life prediction for power cycling was achieved by mapping temperature results from CFD model to finite element model. Parametric studies regarding geometry and material factors were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. It is found that the designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.