Cumulated charging mechanisms at gate processing in high-κ first planar NMOS devices

In this work, different charging mechanisms occurring during processing of the high$-\kappa$ (HK) first gate stack of planar NMOS devices are disentangled by comparing various shapes of gate-on-field antennae. Based on different electrical measurements, the distinct electrical signatures of the charging damage related to these mechanisms are shown. Finally, a qualitative explanation is proposed in terms of oxide traps/charges and plasma bias polarity to account for this difference.