Memory device and method of controlling read level

A memory device and a read level control method is provided. Memory device of the present invention and a memory cell array, the threshold number of the number eojin the number of memory cell counting counter, the three having a threshold voltage which is included in the reference threshold voltage ranges of the plurality of memory cells including a plurality of memory cells second generating a first determination section, and the three eojin number and the new reference threshold voltage ranges based on the comparison result of the threshold number in determining whether to set the read level based on the reference threshold voltage range as compared and including a crystal, one can determine the optimum read level with this. A multi-bit cell, the multi-level cell, the read level, PID control