Design Discussion and Performance Research of the Third-Level Cache in a Multi-socket, Multi-core Microchip

L3cache is an essential part of microchips, which is integrated into most of the microchips such as Intel and AMD chips. FeiTeng serial microchips is an independent research and designed microchip. Our research is based on a 64-cores multi-socket FeiTeng chip. To increase the performance of this chip, L3cache is designed for this chip. This paper first discusses the design of L3cache. Then two crucial evaluation indexes, the latency and bandwidth, are researched. From the simulation, it can be found that when opening L3cache, the latency can reduce 10% at most compared with the latency when closing L3cahce. Moreover, when opening L3cache, the bandwidth can increase twice under the circumstance of accessing a small amount of data. Considering the analysis, it can be concluded that for a multi-socket, multi-core system, L3cache can largely improve the systemic performance.