A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells

Since 22 nm technology node, FinFET technology is an attractive candidate for high-performance and power-efficient applications. This is achieved due to better channel control in FinFET devices obtained by wrapping a metal gate around a thin fin. The new structures used in FinFET technology, as multi-fin and multi-finger, cause new types of defects topologies different from those present in conventional CMOS planar technology. Defect behavior of interconnect open defects in FinFET technology is strongly influenced by the presence of alternative conducting current paths. In this paper, a semi-analytical model for interconnect open defects in FinFET logic cells is presented. The proposed model is able to predict with accuracy the electrical behavior of the logic cell. The proposed model may be used to gain insight into the behavior of the defective FinFET logic cells and to speed-up fault simulation.