Modified circuit for cascaded multilevel inverter with reduced number of switches

This study presents, a modified circuit for symmetrical source multilevel inverter, which consist of cascaded basic unit cells with H-bridge. It requires least number of components as compared to classical and other recent proposed topologies. Also, the suggested circuit reduced the number of on-state switches which will reduced switching loss. The multicarrier pulse width modulation scheme is used to generate pulses for each switch. The simulation results are obtained by MATLAB/Simulink and experimental output also demonstrated using dSPACE real-time controller.